SC417/SC427
25
Applications Information (continued)
Since this 2% error comes from 1/2 of the ripple voltage,
the allowable ripple is 4%, or 42mV for a 1.05V output.
The maximum ripple current of 4.4A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
A
4
.
4
mV
42
I
V
ESR
RIPPLEMAX
RIPPLE
MAX
ESR
MAX
= 9.5 m&
The output capacitance is usually chosen to meet tran-
sient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, determines the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1祍), the output
capacitor must absorb all the inductors stored energy.
This will cause a peak voltage on the capacitor according
to the following equation.
2
OUT
2
PEAK
2
RIPPLEMAX
OUT
MIN
V
V
I
2
1
I
L
COUT
Assuming a peak voltage V
PEAK
of 1.150 (100mV rise upon
load release), and a 10A load release, the required capaci-
tance is shown by the next equation.
2
2
2
MIN
05
.
1
15
.
1
4
.
4
2
1
10
H
88
.
0
COUT
COUT
MIN
= 595礔
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 500mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-V
OUT
. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dI
LOAD
/dt.
Peak inductor current is shown by the next equation.
I
LPK
= I
MAX
+ 1/2 x I
RIPPLEMAX
I
LPK
= 10 + 1/2 x 4.4 = 12.2A
dt
dl
Current
Load
of
change
of
Rate
LOAD
I
MAX
= maximum load release = 10A
T
PK
LOAD
MAX
OUT
LPK
LPK
OUT
V
V
2
dt
dl
I
V
I
L
I
C
Example
s
A
5
.
2
dt
dl
LOAD
This would cause the output current to move from 10A to
0A in 4祍, giving the minimum output capacitance
requirement shown in the following equation.
05
.
1
15
.
1
2
s
1
5
.
2
10
05
.
1
2
.
12
H
88
.
0
2
.
12
C
OUT
C
OUT
= 379 礔
Note that C
OUT
is much smaller in this example, 379礔
compared to 595礔 based on a worst-case load release. To
meet the two design criteria of minimum 379礔 and
maximum 9m& ESR, select two capacitors rated at 220礔
and 15m& ESR.
It is recommended that an additional small capacitor be
placed in parallel with C
OUT
in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
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